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authorClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
commit4c4b6021562c598c4510831bd547edaa97d14dac (patch)
tree7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /passes/memory/memory_share.cc
parentf9946232adf887e5aa4a48c64f88eaa17e424009 (diff)
Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'passes/memory/memory_share.cc')
-rw-r--r--passes/memory/memory_share.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index 35a28d17..b25cf73a 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -143,7 +143,7 @@ struct MemoryShareWorker
non_feedback_nets.insert(bits.begin(), bits.end());
}
- for (auto cell_it : module->cells)
+ for (auto cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
bool ignore_data_port = false;
@@ -650,7 +650,7 @@ struct MemoryShareWorker
std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex;
sigmap_xmux = sigmap;
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;