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authorClifford Wolf <clifford@clifford.at>2014-07-23 20:32:28 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-23 20:32:28 +0200
commitc094c53de83707a5bf1b268640283f1dde235873 (patch)
tree27e480f63e0d34d8cbfcf8fcf29472c198381296 /passes/memory/memory_share.cc
parent8fd8e4a468fb650fe5dcbe892c07010f627e2c2b (diff)
Removed RTLIL::SigSpec::optimize()
Diffstat (limited to 'passes/memory/memory_share.cc')
-rw-r--r--passes/memory/memory_share.cc2
1 files changed, 0 insertions, 2 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index 38eff996..dd2a32ca 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -439,8 +439,6 @@ struct MemoryShareWorker
merged_en.replace(k, cell_en.extract(k, 1));
merged_data.replace(k, cell_data.extract(k, 1));
}
- merged_en.optimize();
- merged_data.optimize();
}
// Connect the new EN and DATA signals and remove the old write port.