diff options
author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-08-30 20:46:20 +0200 |
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committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-08-30 20:46:20 +0200 |
commit | 5033b51947a6ef02cb785b5622e993335efa750a (patch) | |
tree | 7bed18c526bd94917fa2f08e3df12209863698a1 /passes/memory/memory_unpack.cc | |
parent | fefe0fc0430f4f173a25e674708aa0f4f0854b31 (diff) |
New upstream version 0.7+20180830git0b7a184
Diffstat (limited to 'passes/memory/memory_unpack.cc')
-rw-r--r-- | passes/memory/memory_unpack.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index a0fc31b5..49ec6679 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -127,7 +127,7 @@ void handle_module(RTLIL::Design *design, RTLIL::Module *module) struct MemoryUnpackPass : public Pass { MemoryUnpackPass() : Pass("memory_unpack", "unpack multi-port memory cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -137,7 +137,7 @@ struct MemoryUnpackPass : public Pass { log("$memwr cells. It is the counterpart to the memory_collect pass.\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n"); extra_args(args, 1, design); for (auto &mod_it : design->modules_) |