diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-12-27 12:02:57 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-27 12:02:57 +0100 |
| commit | 6c8b0a5fd138d19b47191400f020c2472944f826 (patch) | |
| tree | e67f6b311e40f7b848457e749b6b3e214bf2fa8d /passes/memory | |
| parent | 2c2f8e6e9f4eadbb191df8a8dbeee95443fc9f08 (diff) | |
More dict/pool related changes
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_share.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index f77b304b..ec8df759 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -560,13 +560,13 @@ struct MemoryShareWorker while (!bits_queue.empty()) { - std::set<ModWalker::PortBit> portbits; + pool<ModWalker::PortBit> portbits; modwalker.get_drivers(portbits, bits_queue); bits_queue.clear(); for (auto &pbit : portbits) if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) { - std::set<RTLIL::SigBit> &cell_inputs = modwalker.cell_inputs[pbit.cell]; + pool<RTLIL::SigBit> &cell_inputs = modwalker.cell_inputs[pbit.cell]; bits_queue.insert(cell_inputs.begin(), cell_inputs.end()); sat_cells.insert(pbit.cell); } |