diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 10:18:00 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 11:18:30 +0200 |
| commit | 10e5791c5e5660cb784503d36439ee90d61eb06b (patch) | |
| tree | d7bd3d8f1d0254e14fcf68ce25545f42afab9724 /passes/memory | |
| parent | d088854b47f5f77c6a62be2ba4b895164938d7a2 (diff) | |
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_collect.cc | 2 | ||||
| -rw-r--r-- | passes/memory/memory_dff.cc | 2 | ||||
| -rw-r--r-- | passes/memory/memory_map.cc | 2 | ||||
| -rw-r--r-- | passes/memory/memory_share.cc | 2 | ||||
| -rw-r--r-- | passes/memory/memory_unpack.cc | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index d5995ee0..d2803ae7 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -200,7 +200,7 @@ struct MemoryCollectPass : public Pass { virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { log_header("Executing MEMORY_COLLECT pass (generating $mem cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) handle_module(design, mod_it.second); } diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index bb8b052d..9a1e9679 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -212,7 +212,7 @@ struct MemoryDffPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) handle_module(design, mod_it.second, flag_wr_only); } diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 4bb0c8cc..53394b19 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -317,7 +317,7 @@ struct MemoryMapPass : public Pass { virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) handle_module(design, mod_it.second); } diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index b25cf73a..e61661a2 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -734,7 +734,7 @@ struct MemorySharePass : public Pass { virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) MemoryShareWorker(design, mod_it.second); } diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 48b83f5f..d2b9c0ee 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -102,7 +102,7 @@ struct MemoryUnpackPass : public Pass { virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { log_header("Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) handle_module(design, mod_it.second); } |