diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-10-25 19:30:49 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-25 19:30:49 +0100 |
| commit | 207736b4ee0363ff6714071e64024965916eafc2 (patch) | |
| tree | 31092cfab4323500bc491d8b59deee9e297730d0 /passes/memory | |
| parent | da923c198e770806a4abb749acc75fa337247920 (diff) | |
Import more std:: stuff into Yosys namespace
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_bram.cc | 10 | ||||
| -rw-r--r-- | passes/memory/memory_collect.cc | 2 | ||||
| -rw-r--r-- | passes/memory/memory_share.cc | 2 |
3 files changed, 7 insertions, 7 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index b371578d..f2d9b584 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -387,9 +387,9 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram, if (pi.clkpol > 1) clkpol_wr_ports.insert(pi.clkpol); } - clocks_max = std::max(clocks_max, pi.clocks); - clkpol_max = std::max(clkpol_max, pi.clkpol); - transp_max = std::max(transp_max, pi.transp); + clocks_max = max(clocks_max, pi.clocks); + clkpol_max = max(clkpol_max, pi.clkpol); + transp_max = max(transp_max, pi.transp); } log(" Mapping to bram type %s (variant %d):\n", log_id(bram.name), bram.variant); @@ -977,7 +977,7 @@ void handle_cell(Cell *cell, const rules_t &rules) log("\n"); pool<pair<IdString, int>> failed_brams; - dict<pair<int, int>, std::tuple<int, int, int>> best_rule_cache; + dict<pair<int, int>, tuple<int, int, int>> best_rule_cache; for (int i = 0; i < GetSize(rules.matches); i++) { @@ -1078,7 +1078,7 @@ void handle_cell(Cell *cell, const rules_t &rules) } log(" Storing for later selection.\n"); - best_rule_cache[pair<int, int>(i, vi)] = std::tuple<int, int, int>(match_properties["efficiency"], -match_properties["cells"], -match_properties["acells"]); + best_rule_cache[pair<int, int>(i, vi)] = tuple<int, int, int>(match_properties["efficiency"], -match_properties["cells"], -match_properties["acells"]); next_match_rule: if (or_next_if_better || best_rule_cache.empty()) diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index abd4b124..5c0acb3e 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -64,7 +64,7 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) for (auto &cell_it : module->cells_) { Cell *cell = cell_it.second; if (cell->type.in("$memrd", "$memwr", "$meminit") && memory->name == cell->parameters["\\MEMID"].decode_string()) { - addr_bits = std::max(addr_bits, cell->getParam("\\ABITS").as_int()); + addr_bits = max(addr_bits, cell->getParam("\\ABITS").as_int()); memcells.push_back(cell); } } diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index b8f27025..3a6fd0b4 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -210,7 +210,7 @@ struct MemoryShareWorker if (non_feedback_nets.count(sig_data[i])) goto not_pure_feedback_port; - async_rd_bits[sig_addr].resize(std::max(async_rd_bits.size(), sig_data.size())); + async_rd_bits[sig_addr].resize(max(async_rd_bits.size(), sig_data.size())); for (int i = 0; i < int(sig_data.size()); i++) async_rd_bits[sig_addr][i].insert(sig_data[i]); |