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authorClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
commit4c4b6021562c598c4510831bd547edaa97d14dac (patch)
tree7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /passes/memory
parentf9946232adf887e5aa4a48c64f88eaa17e424009 (diff)
Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'passes/memory')
-rw-r--r--passes/memory/memory_collect.cc2
-rw-r--r--passes/memory/memory_dff.cc6
-rw-r--r--passes/memory/memory_map.cc2
-rw-r--r--passes/memory/memory_share.cc4
-rw-r--r--passes/memory/memory_unpack.cc4
5 files changed, 9 insertions, 9 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index a8caf883..d5995ee0 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -61,7 +61,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
std::vector<RTLIL::Cell*> del_cells;
std::vector<RTLIL::Cell*> memcells;
- for (auto &cell_it : module->cells) {
+ for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if ((cell->type == "$memwr" || cell->type == "$memrd") && cell->parameters["\\MEMID"].decode_string() == memory->name)
memcells.push_back(cell);
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index b63b3aec..bb8b052d 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -38,7 +38,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
if (bit.wire == NULL)
continue;
- for (auto &cell_it : module->cells)
+ for (auto &cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
@@ -120,7 +120,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
- for (auto &cell_it : module->cells) {
+ for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$dff") {
RTLIL::SigSpec new_q = cell->get("\\Q");
@@ -170,7 +170,7 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
static void handle_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_wr_only)
{
- for (auto &cell_it : module->cells) {
+ for (auto &cell_it : module->cells_) {
if (!design->selected(module, cell_it.second))
continue;
if (cell_it.second->type == "$memwr" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 4f166653..4bb0c8cc 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -295,7 +295,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
{
std::vector<RTLIL::Cell*> cells;
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
if (it.second->type == "$mem" && design->selected(module, it.second))
cells.push_back(it.second);
for (auto cell : cells)
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index 35a28d17..b25cf73a 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -143,7 +143,7 @@ struct MemoryShareWorker
non_feedback_nets.insert(bits.begin(), bits.end());
}
- for (auto cell_it : module->cells)
+ for (auto cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
bool ignore_data_port = false;
@@ -650,7 +650,7 @@ struct MemoryShareWorker
std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex;
sigmap_xmux = sigmap;
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc
index f0835076..48b83f5f 100644
--- a/passes/memory/memory_unpack.cc
+++ b/passes/memory/memory_unpack.cc
@@ -80,11 +80,11 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
{
std::vector<RTLIL::IdString> memcells;
- for (auto &cell_it : module->cells)
+ for (auto &cell_it : module->cells_)
if (cell_it.second->type == "$mem" && design->selected(module, cell_it.second))
memcells.push_back(cell_it.first);
for (auto &it : memcells)
- handle_memory(module, module->cells.at(it));
+ handle_memory(module, module->cells_.at(it));
}
struct MemoryUnpackPass : public Pass {