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authorClifford Wolf <clifford@clifford.at>2014-02-02 21:27:26 +0100
committerClifford Wolf <clifford@clifford.at>2014-02-02 21:27:26 +0100
commit67b0ce2578f8c7ade43e8c4e817e4bf4225e78fb (patch)
tree0d45a2210590508aca4408f28a52df0215d03697 /passes/memory
parent83fa65282017cb39a31c6c4c878b9960d8097b66 (diff)
Only generate write-enable $and if WE is not constant 1 in memory_map
Diffstat (limited to 'passes/memory')
-rw-r--r--passes/memory/memory_map.cc33
1 files changed, 18 insertions, 15 deletions
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 45c3933c..9f2b6994 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -273,22 +273,25 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
module->wires[w->name] = w;
c->connections["\\Y"] = RTLIL::SigSpec(w);
- c = new RTLIL::Cell;
- c->name = genid(cell->name, "$wren", i, "", j);
- c->type = "$and";
- c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- c->parameters["\\B_SIGNED"] = RTLIL::Const(0);
- c->parameters["\\A_WIDTH"] = RTLIL::Const(1);
- c->parameters["\\B_WIDTH"] = RTLIL::Const(1);
- c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- c->connections["\\A"] = RTLIL::SigSpec(w);
- c->connections["\\B"] = wr_en;
- module->cells[c->name] = c;
+ if (wr_en != RTLIL::SigSpec(1, 1))
+ {
+ c = new RTLIL::Cell;
+ c->name = genid(cell->name, "$wren", i, "", j);
+ c->type = "$and";
+ c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
+ c->parameters["\\B_SIGNED"] = RTLIL::Const(0);
+ c->parameters["\\A_WIDTH"] = RTLIL::Const(1);
+ c->parameters["\\B_WIDTH"] = RTLIL::Const(1);
+ c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ c->connections["\\A"] = RTLIL::SigSpec(w);
+ c->connections["\\B"] = wr_en;
+ module->cells[c->name] = c;
- w = new RTLIL::Wire;
- w->name = genid(cell->name, "$wren", i, "", j, "$y");
- module->wires[w->name] = w;
- c->connections["\\Y"] = RTLIL::SigSpec(w);
+ w = new RTLIL::Wire;
+ w->name = genid(cell->name, "$wren", i, "", j, "$y");
+ module->wires[w->name] = w;
+ c->connections["\\Y"] = RTLIL::SigSpec(w);
+ }
c = new RTLIL::Cell;
c->name = genid(cell->name, "$wrmux", i, "", j);