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authorClifford Wolf <clifford@clifford.at>2014-07-24 22:47:57 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-24 23:10:58 +0200
commit6aa792c864444324a1b140c2b63bd860f0cc3914 (patch)
tree07b2bf3003864337df616a21374c046ddc352c62 /passes/memory
parent7a608437c65e9646ed229055d61b310e7d93e37e (diff)
Replaced more old SigChunk programming patterns
Diffstat (limited to 'passes/memory')
-rw-r--r--passes/memory/memory_collect.cc10
1 files changed, 5 insertions, 5 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index fec0b407..3ceb5da3 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -147,8 +147,8 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
assert(sig_wr_en.size() == wr_ports * memory->width);
mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports);
- mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.chunks()[0].data : RTLIL::Const(0, 0);
- mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.chunks()[0].data : RTLIL::Const(0, 0);
+ mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0);
+ mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0);
mem->connections["\\WR_CLK"] = sig_wr_clk;
mem->connections["\\WR_ADDR"] = sig_wr_addr;
@@ -162,9 +162,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
assert(sig_rd_data.size() == rd_ports * memory->width);
mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports);
- mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.chunks()[0].data : RTLIL::Const(0, 0);
- mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.chunks()[0].data : RTLIL::Const(0, 0);
- mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.chunks()[0].data : RTLIL::Const(0, 0);
+ mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : RTLIL::Const(0, 0);
+ mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0);
+ mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0);
mem->connections["\\RD_CLK"] = sig_rd_clk;
mem->connections["\\RD_ADDR"] = sig_rd_addr;