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authorClifford Wolf <clifford@clifford.at>2013-10-17 21:00:37 +0200
committerClifford Wolf <clifford@clifford.at>2013-10-17 21:00:37 +0200
commit95dbacefbf9045d191db421af8c6e77bf315d329 (patch)
treed48ab786e1e6b7e908477523593e4d17920946a0 /passes/memory
parentc20571ca5e908d8fe85e41c1632e84de582dc68b (diff)
Fixed bug in synthesis of memories that are never written
Diffstat (limited to 'passes/memory')
-rw-r--r--passes/memory/memory_map.cc9
1 files changed, 7 insertions, 2 deletions
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index b41d3aa2..1651751a 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -121,8 +121,13 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
c->name = genid(cell->name, "", i);
c->type = "$dff";
c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
- c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
- c->connections["\\CLK"] = clocks.extract(0, 1);
+ if (clocks_pol.bits.size() > 0) {
+ c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
+ c->connections["\\CLK"] = clocks.extract(0, 1);
+ } else {
+ c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1);
+ c->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0);
+ }
module->cells[c->name] = c;
RTLIL::Wire *w_in = new RTLIL::Wire;