SigSpec refactoring: renamed chunks and width to __chunks and __width

4 files changed, 32 insertions, 32 deletions

diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 028841f6..6c9e1b77 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -142,16 +142,16 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 	sig_wr_clk_enable.optimize();
 	sig_wr_clk_polarity.optimize();
 
-	assert(sig_wr_clk.width == wr_ports);
-	assert(sig_wr_clk_enable.width == wr_ports && sig_wr_clk_enable.is_fully_const());
-	assert(sig_wr_clk_polarity.width == wr_ports && sig_wr_clk_polarity.is_fully_const());
-	assert(sig_wr_addr.width == wr_ports * addr_bits);
-	assert(sig_wr_data.width == wr_ports * memory->width);
-	assert(sig_wr_en.width == wr_ports * memory->width);
+	assert(sig_wr_clk.__width == wr_ports);
+	assert(sig_wr_clk_enable.__width == wr_ports && sig_wr_clk_enable.is_fully_const());
+	assert(sig_wr_clk_polarity.__width == wr_ports && sig_wr_clk_polarity.is_fully_const());
+	assert(sig_wr_addr.__width == wr_ports * addr_bits);
+	assert(sig_wr_data.__width == wr_ports * memory->width);
+	assert(sig_wr_en.__width == wr_ports * memory->width);
 
 	mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports);
-	mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.chunks[0].data : RTLIL::Const(0, 0);
-	mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.chunks[0].data : RTLIL::Const(0, 0);
+	mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.__chunks[0].data : RTLIL::Const(0, 0);
+	mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.__chunks[0].data : RTLIL::Const(0, 0);
 
 	mem->connections["\\WR_CLK"] = sig_wr_clk;
 	mem->connections["\\WR_ADDR"] = sig_wr_addr;
@@ -162,16 +162,16 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 	sig_rd_clk_polarity.optimize();
 	sig_rd_transparent.optimize();
 
-	assert(sig_rd_clk.width == rd_ports);
-	assert(sig_rd_clk_enable.width == rd_ports && sig_rd_clk_enable.is_fully_const());
-	assert(sig_rd_clk_polarity.width == rd_ports && sig_rd_clk_polarity.is_fully_const());
-	assert(sig_rd_addr.width == rd_ports * addr_bits);
-	assert(sig_rd_data.width == rd_ports * memory->width);
+	assert(sig_rd_clk.__width == rd_ports);
+	assert(sig_rd_clk_enable.__width == rd_ports && sig_rd_clk_enable.is_fully_const());
+	assert(sig_rd_clk_polarity.__width == rd_ports && sig_rd_clk_polarity.is_fully_const());
+	assert(sig_rd_addr.__width == rd_ports * addr_bits);
+	assert(sig_rd_data.__width == rd_ports * memory->width);
 
 	mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports);
-	mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.chunks[0].data : RTLIL::Const(0, 0);
-	mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.chunks[0].data : RTLIL::Const(0, 0);
-	mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.chunks[0].data : RTLIL::Const(0, 0);
+	mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.__chunks[0].data : RTLIL::Const(0, 0);
+	mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.__chunks[0].data : RTLIL::Const(0, 0);
+	mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.__chunks[0].data : RTLIL::Const(0, 0);
 
 	mem->connections["\\RD_CLK"] = sig_rd_clk;
 	mem->connections["\\RD_ADDR"] = sig_rd_addr;
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index e8da6d64..174417bd 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -34,9 +34,9 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 	normalize_sig(module, sig);
 	sig.expand();
 
-	for (size_t i = 0; i < sig.chunks.size(); i++)
+	for (size_t i = 0; i < sig.__chunks.size(); i++)
 	{
-		RTLIL::SigChunk &chunk = sig.chunks[i];
+		RTLIL::SigChunk &chunk = sig.__chunks[i];
 
 		if (chunk.wire == NULL)
 			continue;
@@ -59,11 +59,11 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 			normalize_sig(module, q_norm);
 
 			RTLIL::SigSpec d = q_norm.extract(chunk, &cell->connections[after ? "\\Q" : "\\D"]);
-			if (d.width != 1)
+			if (d.__width != 1)
 				continue;
 
-			assert(d.chunks.size() == 1);
-			chunk = d.chunks[0];
+			assert(d.__chunks.size() == 1);
+			chunk = d.__chunks[0];
 			clk = cell->connections["\\CLK"];
 			clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
 			goto replaced_this_bit;
@@ -125,7 +125,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 
 	RTLIL::Wire *wire = new RTLIL::Wire;
 	wire->name = sstr.str();
-	wire->width = sig.width;
+	wire->width = sig.__width;
 	module->wires[wire->name] = wire;
 
 	RTLIL::SigSpec newsig(wire);
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 10ab6e2f..b848e09e 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -68,7 +68,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"];
 	RTLIL::SigSpec refclock;
 	RTLIL::State refclock_pol = RTLIL::State::Sx;
-	for (int i = 0; i < clocks.width; i++) {
+	for (int i = 0; i < clocks.__width; i++) {
 		RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i * mem_width, mem_width);
 		if (wr_en.is_fully_const() && !wr_en.as_bool()) {
 			static_ports.insert(i);
@@ -89,7 +89,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 					cell->name.c_str(), module->name.c_str(), i);
 			return;
 		}
-		if (refclock.width == 0) {
+		if (refclock.__width == 0) {
 			refclock = clocks.extract(i, 1);
 			refclock_pol = clocks_pol.bits[i];
 		}
@@ -277,12 +277,12 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 			c->connections["\\Y"] = w_seladdr;
 
 			int wr_offset = 0;
-			while (wr_offset < wr_en.width)
+			while (wr_offset < wr_en.__width)
 			{
 				int wr_width = 1;
 				RTLIL::SigSpec wr_bit = wr_en.extract(wr_offset, 1);
 
-				while (wr_offset + wr_width < wr_en.width) {
+				while (wr_offset + wr_width < wr_en.__width) {
 					RTLIL::SigSpec next_wr_bit = wr_en.extract(wr_offset + wr_width, 1);
 					if (next_wr_bit != wr_bit)
 						break;
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index 578007a0..e56d14b6 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -116,7 +116,7 @@ struct MemoryShareWorker
 			created_conditions++;
 		}
 
-		if (terms.width > 1)
+		if (terms.__width > 1)
 			terms = module->ReduceAnd(NEW_ID, terms);
 
 		return conditions_logic_cache[conditions] = terms;
@@ -254,7 +254,7 @@ struct MemoryShareWorker
 		// this is the naive version of the function that does not care about grouping the EN bits.
 
 		RTLIL::SigSpec inv_mask_bits = module->Not(NEW_ID, mask_bits);
-		RTLIL::SigSpec inv_mask_bits_filtered = module->Mux(NEW_ID, RTLIL::SigSpec(RTLIL::State::S1, bits.width), inv_mask_bits, do_mask);
+		RTLIL::SigSpec inv_mask_bits_filtered = module->Mux(NEW_ID, RTLIL::SigSpec(RTLIL::State::S1, bits.__width), inv_mask_bits, do_mask);
 		RTLIL::SigSpec result = module->And(NEW_ID, inv_mask_bits_filtered, bits);
 		return result;
 	}
@@ -269,10 +269,10 @@ struct MemoryShareWorker
 		std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, std::pair<int, std::vector<int>>> groups;
 		RTLIL::SigSpec grouped_bits, grouped_mask_bits;
 
-		for (int i = 0; i < bits.width; i++) {
+		for (int i = 0; i < bits.__width; i++) {
 			std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
 			if (groups.count(key) == 0) {
-				groups[key].first = grouped_bits.width;
+				groups[key].first = grouped_bits.__width;
 				grouped_bits.append_bit(v_bits[i]);
 				grouped_mask_bits.append_bit(v_mask_bits[i]);
 			}
@@ -282,7 +282,7 @@ struct MemoryShareWorker
 		std::vector<RTLIL::SigBit> grouped_result = mask_en_naive(do_mask, grouped_bits, grouped_mask_bits);
 		RTLIL::SigSpec result;
 
-		for (int i = 0; i < bits.width; i++) {
+		for (int i = 0; i < bits.__width; i++) {
 			std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
 			result.append_bit(grouped_result.at(groups.at(key).first));
 		}
@@ -320,7 +320,7 @@ struct MemoryShareWorker
 
 		// Create the new merged_data signal.
 
-		RTLIL::SigSpec new_merged_data(RTLIL::State::Sx, merged_data.width);
+		RTLIL::SigSpec new_merged_data(RTLIL::State::Sx, merged_data.__width);
 
 		RTLIL::SigSpec old_data_set = module->And(NEW_ID, merged_en, merged_data);
 		RTLIL::SigSpec old_data_unset = module->And(NEW_ID, merged_en, module->Not(NEW_ID, merged_data));