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authorClifford Wolf <clifford@clifford.at>2014-07-23 20:32:28 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-23 20:32:28 +0200
commitc094c53de83707a5bf1b268640283f1dde235873 (patch)
tree27e480f63e0d34d8cbfcf8fcf29472c198381296 /passes/memory
parent8fd8e4a468fb650fe5dcbe892c07010f627e2c2b (diff)
Removed RTLIL::SigSpec::optimize()
Diffstat (limited to 'passes/memory')
-rw-r--r--passes/memory/memory_collect.cc7
-rw-r--r--passes/memory/memory_dff.cc1
-rw-r--r--passes/memory/memory_share.cc2
3 files changed, 0 insertions, 10 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 5f06438f..fec0b407 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -139,9 +139,6 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
mem->parameters["\\SIZE"] = RTLIL::Const(memory->size);
mem->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
- sig_wr_clk_enable.optimize();
- sig_wr_clk_polarity.optimize();
-
assert(sig_wr_clk.size() == wr_ports);
assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const());
assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const());
@@ -158,10 +155,6 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
mem->connections["\\WR_DATA"] = sig_wr_data;
mem->connections["\\WR_EN"] = sig_wr_en;
- sig_rd_clk_enable.optimize();
- sig_rd_clk_polarity.optimize();
- sig_rd_transparent.optimize();
-
assert(sig_rd_clk.size() == rd_ports);
assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const());
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index b1f1e22b..56915776 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -69,7 +69,6 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
replaced_this_bit:;
}
- sig.optimize();
return true;
}
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index 38eff996..dd2a32ca 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -439,8 +439,6 @@ struct MemoryShareWorker
merged_en.replace(k, cell_en.extract(k, 1));
merged_data.replace(k, cell_data.extract(k, 1));
}
- merged_en.optimize();
- merged_data.optimize();
}
// Connect the new EN and DATA signals and remove the old write port.