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authorClifford Wolf <clifford@clifford.at>2014-07-19 15:46:11 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-19 15:46:11 +0200
commitefd9604dfb92fda05c3efea67b7c32d812717fa8 (patch)
tree36ee9a483c855898f369b8c9690d951f61438564 /passes/memory
parente0a819dbe507c90e201279db317c2251b3c691eb (diff)
Improved memory_share log messages
Diffstat (limited to 'passes/memory')
-rw-r--r--passes/memory/memory_share.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index cde5f218..dc015f96 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -208,7 +208,7 @@ struct MemoryShareWorker
if (async_rd_bits.empty())
return;
- log("Populating enable bits on write ports of memory %s with aync read feedback:\n", log_id(memid));
+ log("Populating enable bits on write ports of memory %s.%s with aync read feedback:\n", log_id(module), log_id(memid));
for (auto cell : wr_ports)
{
@@ -345,7 +345,7 @@ struct MemoryShareWorker
if (wr_ports.size() <= 1)
return;
- log("Consolidating write ports of memory %s by address:\n", log_id(memid));
+ log("Consolidating write ports of memory %s.%s by address:\n", log_id(module), log_id(memid));
std::map<RTLIL::SigSpec, int> last_port_by_addr;
std::vector<std::vector<bool>> active_bits_on_port;
@@ -501,7 +501,7 @@ struct MemoryShareWorker
port_is_always_active:;
}
- log("Consolidating write ports of memory %s using sat-based resource sharing:\n", log_id(memid));
+ log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", log_id(module), log_id(memid));
bool cache_clk_enable = false;
bool cache_clk_polarity = false;