Refactoring: Renamed RTLIL::Module::wires to wires_

2 files changed, 2 insertions, 2 deletions

diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 32c7e63a..4f166653 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -131,7 +131,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 			c->set("\\D", data_reg_in.back());
 
 			std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i);
-			if (module->wires.count(w_out_name) > 0)
+			if (module->wires_.count(w_out_name) > 0)
 				w_out_name = genid(cell->name, "", i, "$q");
 
 			RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width);
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index df1a2697..35a28d17 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -137,7 +137,7 @@ struct MemoryShareWorker
 		std::map<RTLIL::SigBit, std::set<RTLIL::SigBit>> muxtree_upstream_map;
 		std::set<RTLIL::SigBit> non_feedback_nets;
 
-		for (auto wire_it : module->wires)
+		for (auto wire_it : module->wires_)
 			if (wire_it.second->port_output) {
 				std::vector<RTLIL::SigBit> bits = RTLIL::SigSpec(wire_it.second);
 				non_feedback_nets.insert(bits.begin(), bits.end());