diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:14:02 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:14:02 +0200 |
| commit | 3f4e3ca8ad480c2e73e2072ada77078ffd95e08f (patch) | |
| tree | 3117545be59991dc797086c5d273ed97220c75ef /passes/opt/opt_const.cc | |
| parent | 97a59851a6c411ccb06162d4b31725bf89262378 (diff) | |
More RTLIL::Cell API usage cleanups
Diffstat (limited to 'passes/opt/opt_const.cc')
| -rw-r--r-- | passes/opt/opt_const.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 000a9ec2..67218600 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -94,7 +94,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool(); RTLIL::SigSpec sig_a = sigmap(cell->get("\\A")); - RTLIL::SigSpec sig_b = sigmap(cell->connections().at(b_name)); + RTLIL::SigSpec sig_b = sigmap(cell->get(b_name)); RTLIL::SigSpec sig_y = sigmap(cell->get("\\Y")); if (extend_u0) { |