summaryrefslogtreecommitdiff
path: root/passes/opt/opt_const.cc
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2014-12-26 10:53:21 +0100
committerClifford Wolf <clifford@clifford.at>2014-12-26 10:53:21 +0100
commita6c96b986be313368b4fa03eba5cf6987448100c (patch)
treeedb56a97a9c64376e1ee920133c46aeefe539ef1 /passes/opt/opt_const.cc
parente8c12e5f0c49cca4dd54da12003bd010a488aee3 (diff)
Added Yosys::{dict,nodict,vector} container types
Diffstat (limited to 'passes/opt/opt_const.cc')
-rw-r--r--passes/opt/opt_const.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 5bac76cf..7f800bde 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -196,11 +196,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
ct_combinational.setup_stdcells();
SigMap assign_map(module);
- std::map<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
+ dict<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
- std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
- std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
+ dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
+ dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
for (auto cell : module->cells())
if (design->selected(module, cell) && cell->type[0] == '$') {