Imported yosys 0.7

1 files changed, 27 insertions, 8 deletions

diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index fa954afa..922f086f 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -29,6 +29,7 @@ PRIVATE_NAMESPACE_BEGIN
 SigMap assign_map, dff_init_map;
 SigSet<RTLIL::Cell*> mux_drivers;
 dict<SigBit, pool<SigBit>> init_attributes;
+bool keepdc;
 
 void remove_init_attr(SigSpec sig)
 {
@@ -71,7 +72,11 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 	RTLIL::SigSpec sig_d, sig_q, sig_c, sig_r;
 	RTLIL::Const val_cp, val_rp, val_rv;
 
-	if (dff->type == "$_DFF_N_" || dff->type == "$_DFF_P_") {
+	if (dff->type == "$_FF_") {
+		sig_d = dff->getPort("\\D");
+		sig_q = dff->getPort("\\Q");
+	}
+	else if (dff->type == "$_DFF_N_" || dff->type == "$_DFF_P_") {
 		sig_d = dff->getPort("\\D");
 		sig_q = dff->getPort("\\Q");
 		sig_c = dff->getPort("\\C");
@@ -89,6 +94,10 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
 		val_rv = RTLIL::Const(dff->type[8] == '1', 1);
 	}
+	else if (dff->type == "$ff") {
+		sig_d = dff->getPort("\\D");
+		sig_q = dff->getPort("\\Q");
+	}
 	else if (dff->type == "$dff") {
 		sig_d = dff->getPort("\\D");
 		sig_q = dff->getPort("\\Q");
@@ -115,12 +124,12 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 	bool has_init = false;
 	RTLIL::Const val_init;
 	for (auto bit : dff_init_map(sig_q).to_sigbit_vector()) {
-		if (bit.wire == NULL)
+		if (bit.wire == NULL || keepdc)
 			has_init = true;
 		val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx);
 	}
 
-	if (dff->type == "$dff" && mux_drivers.has(sig_d)) {
+	if (dff->type.in("$ff", "$dff") && mux_drivers.has(sig_d)) {
 		std::set<RTLIL::Cell*> muxes;
 		mux_drivers.find(sig_d, muxes);
 		for (auto mux : muxes) {
@@ -137,7 +146,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		}
 	}
 
-	if (sig_c.is_fully_const() && (!sig_r.size() || !has_init || val_init == val_rv)) {
+	if (!sig_c.empty() && sig_c.is_fully_const() && (!sig_r.size() || !has_init || val_init == val_rv)) {
 		if (val_rv.bits.size() == 0)
 			val_rv = val_init;
 		mod->connect(sig_q, val_rv);
@@ -182,7 +191,7 @@ struct OptRmdffPass : public Pass {
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    opt_rmdff [selection]\n");
+		log("    opt_rmdff [-keepdc] [selection]\n");
 		log("\n");
 		log("This pass identifies flip-flops with constant inputs and replaces them with\n");
 		log("a constant driver.\n");
@@ -193,7 +202,17 @@ struct OptRmdffPass : public Pass {
 		int total_count = 0, total_initdrv = 0;
 		log_header(design, "Executing OPT_RMDFF pass (remove dff with constant values).\n");
 
-		extra_args(args, 1, design);
+		keepdc = false;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-keepdc") {
+				keepdc = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
 
 		for (auto module : design->selected_modules())
 		{
@@ -243,10 +262,10 @@ struct OptRmdffPass : public Pass {
 				if (!design->selected(module, cell))
 					continue;
 
-				if (cell->type.in("$_DFF_N_", "$_DFF_P_",
+				if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_",
 						"$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
 						"$_DFF_PN0_", "$_DFF_PN1_", "$_DFF_PP0_", "$_DFF_PP1_",
-						"$dff", "$adff"))
+						"$ff", "$dff", "$adff"))
 					dff_list.push_back(cell->name);
 
 				if (cell->type == "$dlatch")