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authorClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
commit4c4b6021562c598c4510831bd547edaa97d14dac (patch)
tree7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /passes/opt/opt_share.cc
parentf9946232adf887e5aa4a48c64f88eaa17e424009 (diff)
Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'passes/opt/opt_share.cc')
-rw-r--r--passes/opt/opt_share.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index c91f037d..304ba9f8 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -248,8 +248,8 @@ struct OptShareWorker
cell_hash_cache.clear();
#endif
std::vector<RTLIL::Cell*> cells;
- cells.reserve(module->cells.size());
- for (auto &it : module->cells) {
+ cells.reserve(module->cells_.size());
+ for (auto &it : module->cells_) {
if (ct.cell_known(it.second->type) && design->selected(module, it.second))
cells.push_back(it.second);
}