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authorClifford Wolf <clifford@clifford.at>2014-07-26 15:57:57 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 15:58:23 +0200
commitf8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (patch)
treee4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /passes/opt/opt_share.cc
parentb7dda723022ad00c6c0089be888eab319953faa8 (diff)
Manual fixes for new cell connections API
Diffstat (limited to 'passes/opt/opt_share.cc')
-rw-r--r--passes/opt/opt_share.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index 8412f929..4f733a37 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -263,7 +263,7 @@ struct OptShareWorker
log(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
for (auto &it : cell->connections()) {
if (ct.cell_output(cell->type, it.first)) {
- RTLIL::SigSpec other_sig = sharemap[cell]->connections()[it.first];
+ RTLIL::SigSpec other_sig = sharemap[cell]->get(it.first);
log(" Redirecting output %s: %s = %s\n", it.first.c_str(),
log_signal(it.second), log_signal(other_sig));
module->connect(RTLIL::SigSig(it.second, other_sig));