diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-07-28 11:08:55 +0200 |
---|---|---|
committer | Clifford Wolf <clifford@clifford.at> | 2014-07-28 11:27:48 +0200 |
commit | 7bd2d1064f2eceddc3c93c121c4154a2f594a040 (patch) | |
tree | 563de1df5e323d0f217a51e29acb56c9e9f1327d /passes/opt | |
parent | d86a25f145012ccb6b2048af3aae22f13b97b505 (diff) |
Using log_assert() instead of assert()
Diffstat (limited to 'passes/opt')
-rw-r--r-- | passes/opt/opt_clean.cc | 3 | ||||
-rw-r--r-- | passes/opt/opt_const.cc | 3 | ||||
-rw-r--r-- | passes/opt/opt_muxtree.cc | 1 | ||||
-rw-r--r-- | passes/opt/opt_reduce.cc | 1 | ||||
-rw-r--r-- | passes/opt/opt_share.cc | 1 |
5 files changed, 2 insertions, 7 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 6c20bddb..4182c6f5 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -23,7 +23,6 @@ #include "kernel/log.h" #include "kernel/celltypes.h" #include <stdlib.h> -#include <assert.h> #include <stdio.h> #include <set> @@ -227,7 +226,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep")) { maybe_del_wires.push_back(wire); } else { - assert(SIZE(s1) == SIZE(s2)); + log_assert(SIZE(s1) == SIZE(s2)); RTLIL::SigSig new_conn; for (int i = 0; i < SIZE(s1); i++) if (s1[i] != s2[i]) { diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 7578f192..254fe5bb 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -24,7 +24,6 @@ #include "kernel/toposort.h" #include "kernel/log.h" #include <stdlib.h> -#include <assert.h> #include <stdio.h> #include <algorithm> @@ -495,7 +494,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec new_a, new_b; - assert(SIZE(a) == SIZE(b)); + log_assert(SIZE(a) == SIZE(b)); for (int i = 0; i < SIZE(a); i++) { if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) { cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type); diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 73baaf90..de12542d 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -23,7 +23,6 @@ #include "kernel/log.h" #include "kernel/celltypes.h" #include <stdlib.h> -#include <assert.h> #include <stdio.h> #include <set> diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index b2b7cc8b..8aadd1f2 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -24,7 +24,6 @@ #include "kernel/celltypes.h" #include "libs/sha1/sha1.h" #include <stdlib.h> -#include <assert.h> #include <stdio.h> #include <set> diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 45130229..ad6e1a74 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -24,7 +24,6 @@ #include "kernel/celltypes.h" #include "libs/sha1/sha1.h" #include <stdlib.h> -#include <assert.h> #include <stdio.h> #include <set> |