diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-10-03 10:12:28 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-10-03 10:12:28 +0200 |
| commit | c3e779a65f285afa123b990f3a717a7ae8e028f5 (patch) | |
| tree | 5a095488026f2371f1a13556478af7f5e7cd3b6c /passes/opt | |
| parent | 600c6cb013b6cf872f3b3f01c7d88df2092e84d9 (diff) | |
Added $_BUF_ cell type
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_clean.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 15bbf54e..004a2078 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -295,8 +295,8 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose) std::vector<RTLIL::Cell*> delcells; for (auto cell : module->cells()) - if (cell->type == "$pos") { - bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); + if (cell->type.in("$pos", "$_BUF_")) { + bool is_signed = cell->type == "$pos" && cell->getParam("\\A_SIGNED").as_bool(); RTLIL::SigSpec a = cell->getPort("\\A"); RTLIL::SigSpec y = cell->getPort("\\Y"); a.extend_u0(SIZE(y), is_signed); |