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authorClifford Wolf <clifford@clifford.at>2013-12-27 15:10:07 +0100
committerClifford Wolf <clifford@clifford.at>2013-12-27 15:18:14 +0100
commitc9699fe76deb13209d61af461d9ce850a5113c8d (patch)
tree1ab3e4a5539ae6c66633b4ff2afa9a04f49e1de9 /passes/opt
parent72026a934ecfd072b2e0964a12ba4fdafc0f276e (diff)
More $eq/$ne/$eqx/$nex fixes in opt_const
Diffstat (limited to 'passes/opt')
-rw-r--r--passes/opt/opt_const.cc9
1 files changed, 8 insertions, 1 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index d84910ee..a3f3ee41 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -160,6 +160,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
assert(a.chunks.size() == b.chunks.size());
for (size_t i = 0; i < a.chunks.size(); i++) {
+ if (a.chunks[i].wire == NULL && b.chunks[i].wire == NULL &&
+ a.chunks[i].data.bits[0] != b.chunks[i].data.bits[0]) {
+ RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1);
+ new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
+ replace_cell(module, cell, "empty", "\\Y", new_y);
+ goto next_cell;
+ }
if (cell->type == "$eq" || cell->type == "$ne") {
if (a.chunks[i].wire == NULL && a.chunks[i].data.bits[0] > RTLIL::State::S1)
continue;
@@ -173,7 +180,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
if (new_a.width == 0) {
- RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type == "$eq" ? RTLIL::State::S1 : RTLIL::State::S0);
+ RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S1 : RTLIL::State::S0);
new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
replace_cell(module, cell, "empty", "\\Y", new_y);
goto next_cell;