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authorClifford Wolf <clifford@clifford.at>2013-03-25 17:13:14 +0100
committerClifford Wolf <clifford@clifford.at>2013-03-25 17:13:14 +0100
commit227520f94d5fe0eb983889b61ed9b72640f1b4f4 (patch)
treeab39e242d3344e6a2b1712e99aba14f09c19d79c /passes/proc/proc_arst.cc
parent37379648097cb01f6181324c69cabb677ecc06ca (diff)
Added nosync attribute and some async reset related fixes
Diffstat (limited to 'passes/proc/proc_arst.cc')
-rw-r--r--passes/proc/proc_arst.cc5
1 files changed, 5 insertions, 0 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index 62dfebae..d0a0d864 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -150,6 +150,11 @@ static void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_m
for (auto &action : sync->actions) {
RTLIL::SigSpec rspec = action.second;
RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.width);
+ rspec.expand(), rval.expand();
+ for (int i = 0; i < int(rspec.chunks.size()); i++)
+ if (rspec.chunks[i].wire == NULL)
+ rval.chunks[i] = rspec.chunks[i];
+ rspec.optimize(), rval.optimize();
RTLIL::SigSpec last_rval;
for (int count = 0; rval != last_rval; count++) {
last_rval = rval;