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authorClifford Wolf <clifford@clifford.at>2014-07-27 10:18:00 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 11:18:30 +0200
commit10e5791c5e5660cb784503d36439ee90d61eb06b (patch)
treed7bd3d8f1d0254e14fcf68ce25545f42afab9724 /passes/proc/proc_dff.cc
parentd088854b47f5f77c6a62be2ba4b895164938d7a2 (diff)
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'passes/proc/proc_dff.cc')
-rw-r--r--passes/proc/proc_dff.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index cfd2eb7a..7bd909a6 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -371,7 +371,7 @@ struct ProcDffPass : public Pass {
extra_args(args, 1, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second)) {
ConstEval ce(mod_it.second);
for (auto &proc_it : mod_it.second->processes)