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authorClifford Wolf <clifford@clifford.at>2014-07-31 13:19:47 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-31 13:19:47 +0200
commit1cb25c05b37b0172dbc50e140fe20f25d973dd8a (patch)
tree4bccb9f45ccad05346697c79afca9a1b21dced9c /passes/proc/proc_dff.cc
parent1202f7aa4bb0f9afde157ebc4701d64e7e38abd8 (diff)
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Diffstat (limited to 'passes/proc/proc_dff.cc')
-rw-r--r--passes/proc/proc_dff.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index 91cafe3b..d894b442 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -122,7 +122,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
}
std::stringstream sstr;
- sstr << "$procdff$" << (RTLIL::autoidx++);
+ sstr << "$procdff$" << (autoidx++);
RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
cell->attributes = proc->attributes;
@@ -144,7 +144,7 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec
bool clk_polarity, bool set_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec set, RTLIL::Process *proc)
{
std::stringstream sstr;
- sstr << "$procdff$" << (RTLIL::autoidx++);
+ sstr << "$procdff$" << (autoidx++);
RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.size());
RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size());
@@ -191,7 +191,7 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_
bool clk_polarity, bool arst_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec *arst, RTLIL::Process *proc)
{
std::stringstream sstr;
- sstr << "$procdff$" << (RTLIL::autoidx++);
+ sstr << "$procdff$" << (autoidx++);
RTLIL::Cell *cell = mod->addCell(sstr.str(), arst ? "$adff" : "$dff");
cell->attributes = proc->attributes;