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authorClifford Wolf <clifford@clifford.at>2014-07-24 22:47:57 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-24 23:10:58 +0200
commit6aa792c864444324a1b140c2b63bd860f0cc3914 (patch)
tree07b2bf3003864337df616a21374c046ddc352c62 /passes/proc/proc_init.cc
parent7a608437c65e9646ed229055d61b310e7d93e37e (diff)
Replaced more old SigChunk programming patterns
Diffstat (limited to 'passes/proc/proc_init.cc')
-rw-r--r--passes/proc/proc_init.cc19
1 files changed, 9 insertions, 10 deletions
diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc
index 4c9b6bcd..5976c216 100644
--- a/passes/proc/proc_init.cc
+++ b/passes/proc/proc_init.cc
@@ -58,16 +58,15 @@ static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs));
int offset = 0;
- for (size_t i = 0; i < lhs.chunks().size(); i++) {
- if (lhs.chunks()[i].wire == NULL)
- continue;
- RTLIL::Wire *wire = lhs.chunks()[i].wire;
- RTLIL::SigSpec value = rhs.extract(offset, lhs.chunks()[i].width);
- if (value.size() != wire->width)
- log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.chunks()[i]), log_signal(value));
- log(" Setting init value: %s = %s\n", log_signal(wire), log_signal(value));
- wire->attributes["\\init"] = value.as_const();
- offset += wire->width;
+ for (auto &lhs_c : lhs.chunks()) {
+ if (lhs_c.wire != NULL) {
+ RTLIL::SigSpec value = rhs.extract(offset, lhs_c.width);
+ if (value.size() != lhs_c.wire->width)
+ log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs_c), log_signal(value));
+ log(" Setting init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(value));
+ lhs_c.wire->attributes["\\init"] = value.as_const();
+ }
+ offset += lhs_c.width;
}
}
}