Renamed RTLIL::{Module,Cell}::connections to connections_

3 files changed, 82 insertions, 82 deletions

diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index 145abfa4..ce313360 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -35,40 +35,40 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp
 
 	for (auto &cell_it : mod->cells) {
 		RTLIL::Cell *cell = cell_it.second;
-		if (cell->type == "$reduce_or" && cell->connections["\\Y"] == signal)
-			return check_signal(mod, cell->connections["\\A"], ref, polarity);
-		if (cell->type == "$reduce_bool" && cell->connections["\\Y"] == signal)
-			return check_signal(mod, cell->connections["\\A"], ref, polarity);
-		if (cell->type == "$logic_not" && cell->connections["\\Y"] == signal) {
+		if (cell->type == "$reduce_or" && cell->connections_["\\Y"] == signal)
+			return check_signal(mod, cell->connections_["\\A"], ref, polarity);
+		if (cell->type == "$reduce_bool" && cell->connections_["\\Y"] == signal)
+			return check_signal(mod, cell->connections_["\\A"], ref, polarity);
+		if (cell->type == "$logic_not" && cell->connections_["\\Y"] == signal) {
 			polarity = !polarity;
-			return check_signal(mod, cell->connections["\\A"], ref, polarity);
+			return check_signal(mod, cell->connections_["\\A"], ref, polarity);
 		}
-		if (cell->type == "$not" && cell->connections["\\Y"] == signal) {
+		if (cell->type == "$not" && cell->connections_["\\Y"] == signal) {
 			polarity = !polarity;
-			return check_signal(mod, cell->connections["\\A"], ref, polarity);
+			return check_signal(mod, cell->connections_["\\A"], ref, polarity);
 		}
-		if ((cell->type == "$eq" || cell->type == "$eqx") && cell->connections["\\Y"] == signal) {
-			if (cell->connections["\\A"].is_fully_const()) {
-				if (!cell->connections["\\A"].as_bool())
+		if ((cell->type == "$eq" || cell->type == "$eqx") && cell->connections_["\\Y"] == signal) {
+			if (cell->connections_["\\A"].is_fully_const()) {
+				if (!cell->connections_["\\A"].as_bool())
 					polarity = !polarity;
-				return check_signal(mod, cell->connections["\\B"], ref, polarity);
+				return check_signal(mod, cell->connections_["\\B"], ref, polarity);
 			}
-			if (cell->connections["\\B"].is_fully_const()) {
-				if (!cell->connections["\\B"].as_bool())
+			if (cell->connections_["\\B"].is_fully_const()) {
+				if (!cell->connections_["\\B"].as_bool())
 					polarity = !polarity;
-				return check_signal(mod, cell->connections["\\A"], ref, polarity);
+				return check_signal(mod, cell->connections_["\\A"], ref, polarity);
 			}
 		}
-		if ((cell->type == "$ne" || cell->type == "$nex") && cell->connections["\\Y"] == signal) {
-			if (cell->connections["\\A"].is_fully_const()) {
-				if (cell->connections["\\A"].as_bool())
+		if ((cell->type == "$ne" || cell->type == "$nex") && cell->connections_["\\Y"] == signal) {
+			if (cell->connections_["\\A"].is_fully_const()) {
+				if (cell->connections_["\\A"].as_bool())
 					polarity = !polarity;
-				return check_signal(mod, cell->connections["\\B"], ref, polarity);
+				return check_signal(mod, cell->connections_["\\B"], ref, polarity);
 			}
-			if (cell->connections["\\B"].is_fully_const()) {
-				if (cell->connections["\\B"].as_bool())
+			if (cell->connections_["\\B"].is_fully_const()) {
+				if (cell->connections_["\\B"].as_bool())
 					polarity = !polarity;
-				return check_signal(mod, cell->connections["\\A"], ref, polarity);
+				return check_signal(mod, cell->connections_["\\A"], ref, polarity);
 			}
 		}
 	}
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index 876adb0d..9d2c897e 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -77,8 +77,8 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
 			cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 			cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
 			cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-			cell->connections["\\A"] = sync_low_signals;
-			cell->connections["\\Y"] = sync_low_signals = mod->addWire(NEW_ID);
+			cell->connections_["\\A"] = sync_low_signals;
+			cell->connections_["\\Y"] = sync_low_signals = mod->addWire(NEW_ID);
 		}
 
 		if (sync_low_signals.size() > 0) {
@@ -86,9 +86,9 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
 			cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 			cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
 			cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-			cell->connections["\\A"] = sync_low_signals;
-			cell->connections["\\Y"] = mod->addWire(NEW_ID);
-			sync_high_signals.append(cell->connections["\\Y"]);
+			cell->connections_["\\A"] = sync_low_signals;
+			cell->connections_["\\Y"] = mod->addWire(NEW_ID);
+			sync_high_signals.append(cell->connections_["\\Y"]);
 		}
 
 		if (sync_high_signals.size() > 1) {
@@ -96,30 +96,30 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
 			cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 			cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size());
 			cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-			cell->connections["\\A"] = sync_high_signals;
-			cell->connections["\\Y"] = sync_high_signals = mod->addWire(NEW_ID);
+			cell->connections_["\\A"] = sync_high_signals;
+			cell->connections_["\\Y"] = sync_high_signals = mod->addWire(NEW_ID);
 		}
 
 		RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not");
 		inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 		inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size());
 		inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size());
-		inv_cell->connections["\\A"] = sync_value;
-		inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size());
+		inv_cell->connections_["\\A"] = sync_value;
+		inv_cell->connections_["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size());
 
 		RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux");
 		mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
-		mux_set_cell->connections["\\A"] = sig_sr_set;
-		mux_set_cell->connections["\\B"] = sync_value;
-		mux_set_cell->connections["\\S"] = sync_high_signals;
-		mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size());
+		mux_set_cell->connections_["\\A"] = sig_sr_set;
+		mux_set_cell->connections_["\\B"] = sync_value;
+		mux_set_cell->connections_["\\S"] = sync_high_signals;
+		mux_set_cell->connections_["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size());
 
 		RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux");
 		mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
-		mux_clr_cell->connections["\\A"] = sig_sr_clr;
-		mux_clr_cell->connections["\\B"] = sync_value_inv;
-		mux_clr_cell->connections["\\S"] = sync_high_signals;
-		mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size());
+		mux_clr_cell->connections_["\\A"] = sig_sr_clr;
+		mux_clr_cell->connections_["\\B"] = sync_value_inv;
+		mux_clr_cell->connections_["\\S"] = sync_high_signals;
+		mux_clr_cell->connections_["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size());
 	}
 
 	std::stringstream sstr;
@@ -131,11 +131,11 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
 	cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
 	cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
 	cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
-	cell->connections["\\D"] = sig_d;
-	cell->connections["\\Q"] = sig_q;
-	cell->connections["\\CLK"] = clk;
-	cell->connections["\\SET"] = sig_sr_set;
-	cell->connections["\\CLR"] = sig_sr_clr;
+	cell->connections_["\\D"] = sig_d;
+	cell->connections_["\\Q"] = sig_q;
+	cell->connections_["\\CLK"] = clk;
+	cell->connections_["\\SET"] = sig_sr_set;
+	cell->connections_["\\CLR"] = sig_sr_clr;
 
 	log("  created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
 			cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
@@ -155,22 +155,22 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec
 	inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 	inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size());
 	inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size());
-	inv_set->connections["\\A"] = sig_set;
-	inv_set->connections["\\Y"] = sig_set_inv;
+	inv_set->connections_["\\A"] = sig_set;
+	inv_set->connections_["\\Y"] = sig_set_inv;
 
 	RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux");
 	mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
-	mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size());
-	mux_sr_set->connections[set_polarity ? "\\B" : "\\A"] = sig_set;
-	mux_sr_set->connections["\\Y"] = sig_sr_set;
-	mux_sr_set->connections["\\S"] = set;
+	mux_sr_set->connections_[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size());
+	mux_sr_set->connections_[set_polarity ? "\\B" : "\\A"] = sig_set;
+	mux_sr_set->connections_["\\Y"] = sig_sr_set;
+	mux_sr_set->connections_["\\S"] = set;
 
 	RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux");
 	mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
-	mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size());
-	mux_sr_clr->connections[set_polarity ? "\\B" : "\\A"] = sig_set_inv;
-	mux_sr_clr->connections["\\Y"] = sig_sr_clr;
-	mux_sr_clr->connections["\\S"] = set;
+	mux_sr_clr->connections_[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size());
+	mux_sr_clr->connections_[set_polarity ? "\\B" : "\\A"] = sig_set_inv;
+	mux_sr_clr->connections_["\\Y"] = sig_sr_clr;
+	mux_sr_clr->connections_["\\S"] = set;
 
 	RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
 	cell->attributes = proc->attributes;
@@ -178,11 +178,11 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec
 	cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
 	cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
 	cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
-	cell->connections["\\D"] = sig_in;
-	cell->connections["\\Q"] = sig_out;
-	cell->connections["\\CLK"] = clk;
-	cell->connections["\\SET"] = sig_sr_set;
-	cell->connections["\\CLR"] = sig_sr_clr;
+	cell->connections_["\\D"] = sig_in;
+	cell->connections_["\\Q"] = sig_out;
+	cell->connections_["\\CLK"] = clk;
+	cell->connections_["\\SET"] = sig_sr_set;
+	cell->connections_["\\CLR"] = sig_sr_clr;
 
 	log("  created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(),
 			clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
@@ -204,11 +204,11 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_
 	}
 	cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
 
-	cell->connections["\\D"] = sig_in;
-	cell->connections["\\Q"] = sig_out;
+	cell->connections_["\\D"] = sig_in;
+	cell->connections_["\\Q"] = sig_out;
 	if (arst)
-		cell->connections["\\ARST"] = *arst;
-	cell->connections["\\CLK"] = clk;
+		cell->connections_["\\ARST"] = *arst;
+	cell->connections_["\\CLK"] = clk;
 
 	log("  created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
 	if (arst)
@@ -296,9 +296,9 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 				cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size());
 				cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size());
 				cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-				cell->connections["\\A"] = inputs;
-				cell->connections["\\B"] = compare;
-				cell->connections["\\Y"] = sync_level->signal;
+				cell->connections_["\\A"] = inputs;
+				cell->connections_["\\B"] = compare;
+				cell->connections_["\\Y"] = sync_level->signal;
 
 				many_async_rules.clear();
 			}
@@ -322,7 +322,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 			if (sync_edge || sync_level || many_async_rules.size() > 0)
 				log_error("Mixed always event with edge and/or level sensitive events!\n");
 			log("  created direct connection (no actual register cell created).\n");
-			mod->connections.push_back(RTLIL::SigSig(sig, insig));
+			mod->connections_.push_back(RTLIL::SigSig(sig, insig));
 			continue;
 		}
 
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index 5bb1ab94..2cde749a 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -81,7 +81,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 
 		if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1))
 		{
-			mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig));
+			mod->connections_.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig));
 		}
 		else
 		{
@@ -96,9 +96,9 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 			eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size());
 			eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
 
-			eq_cell->connections["\\A"] = sig;
-			eq_cell->connections["\\B"] = comp;
-			eq_cell->connections["\\Y"] = RTLIL::SigSpec(cmp_wire, cmp_wire->width++);
+			eq_cell->connections_["\\A"] = sig;
+			eq_cell->connections_["\\B"] = comp;
+			eq_cell->connections_["\\Y"] = RTLIL::SigSpec(cmp_wire, cmp_wire->width++);
 		}
 	}
 
@@ -122,8 +122,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 		any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width);
 		any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
 
-		any_cell->connections["\\A"] = cmp_wire;
-		any_cell->connections["\\Y"] = RTLIL::SigSpec(ctrl_wire);
+		any_cell->connections_["\\A"] = cmp_wire;
+		any_cell->connections_["\\Y"] = RTLIL::SigSpec(ctrl_wire);
 	}
 
 	return RTLIL::SigSpec(ctrl_wire);
@@ -157,10 +157,10 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 	mux_cell->attributes = sw->attributes;
 
 	mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size());
-	mux_cell->connections["\\A"] = else_signal;
-	mux_cell->connections["\\B"] = when_signal;
-	mux_cell->connections["\\S"] = ctrl_sig;
-	mux_cell->connections["\\Y"] = RTLIL::SigSpec(result_wire);
+	mux_cell->connections_["\\A"] = else_signal;
+	mux_cell->connections_["\\B"] = when_signal;
+	mux_cell->connections_["\\S"] = ctrl_sig;
+	mux_cell->connections_["\\Y"] = RTLIL::SigSpec(result_wire);
 
 	last_mux_cell = mux_cell;
 	return RTLIL::SigSpec(result_wire);
@@ -169,14 +169,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw)
 {
 	assert(last_mux_cell != NULL);
-	assert(when_signal.size() == last_mux_cell->connections["\\A"].size());
+	assert(when_signal.size() == last_mux_cell->connections_["\\A"].size());
 
 	RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw);
 	assert(ctrl_sig.size() == 1);
 	last_mux_cell->type = "$pmux";
-	last_mux_cell->connections["\\S"].append(ctrl_sig);
-	last_mux_cell->connections["\\B"].append(when_signal);
-	last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].size();
+	last_mux_cell->connections_["\\S"].append(ctrl_sig);
+	last_mux_cell->connections_["\\B"].append(when_signal);
+	last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections_["\\S"].size();
 }
 
 static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval)
@@ -256,7 +256,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc)
 		log("  creating decoder for signal `%s'.\n", log_signal(sig));
 
 		RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.size()));
-		mod->connections.push_back(RTLIL::SigSig(sig, value));
+		mod->connections_.push_back(RTLIL::SigSig(sig, value));
 	}
 }