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authorClifford Wolf <clifford@clifford.at>2014-07-27 10:41:42 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 11:32:42 +0200
commit49f72421d5ec499da5da713466e058aae2a67436 (patch)
tree518c98c7f0fe21344f61b04e21b00d8309ae8d0b /passes/proc
parent675cb93da9e67f5c2fe8a3760de5893176ea906d (diff)
Using new obj iterator API in a few places
Diffstat (limited to 'passes/proc')
-rw-r--r--passes/proc/proc_arst.cc25
-rw-r--r--passes/proc/proc_clean.cc16
-rw-r--r--passes/proc/proc_dff.cc12
-rw-r--r--passes/proc/proc_init.cc10
-rw-r--r--passes/proc/proc_mux.cc10
-rw-r--r--passes/proc/proc_rmdead.cc10
6 files changed, 44 insertions, 39 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index e8439477..676469fe 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -33,20 +33,24 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp
if (signal == ref)
return true;
- for (auto &cell_it : mod->cells_) {
- RTLIL::Cell *cell = cell_it.second;
+ for (auto cell : mod->cells())
+ {
if (cell->type == "$reduce_or" && cell->get("\\Y") == signal)
return check_signal(mod, cell->get("\\A"), ref, polarity);
+
if (cell->type == "$reduce_bool" && cell->get("\\Y") == signal)
return check_signal(mod, cell->get("\\A"), ref, polarity);
+
if (cell->type == "$logic_not" && cell->get("\\Y") == signal) {
polarity = !polarity;
return check_signal(mod, cell->get("\\A"), ref, polarity);
}
+
if (cell->type == "$not" && cell->get("\\Y") == signal) {
polarity = !polarity;
return check_signal(mod, cell->get("\\A"), ref, polarity);
}
+
if ((cell->type == "$eq" || cell->type == "$eqx") && cell->get("\\Y") == signal) {
if (cell->get("\\A").is_fully_const()) {
if (!cell->get("\\A").as_bool())
@@ -59,6 +63,7 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp
return check_signal(mod, cell->get("\\A"), ref, polarity);
}
}
+
if ((cell->type == "$ne" || cell->type == "$nex") && cell->get("\\Y") == signal) {
if (cell->get("\\A").is_fully_const()) {
if (cell->get("\\A").as_bool())
@@ -236,14 +241,14 @@ struct ProcArstPass : public Pass {
extra_args(args, argidx, design);
- for (auto &mod_it : design->modules_)
- if (design->selected(mod_it.second)) {
- SigMap assign_map(mod_it.second);
- for (auto &proc_it : mod_it.second->processes) {
- if (!design->selected(mod_it.second, proc_it.second))
+ for (auto mod : design->modules())
+ if (design->selected(mod)) {
+ SigMap assign_map(mod);
+ for (auto &proc_it : mod->processes) {
+ if (!design->selected(mod, proc_it.second))
continue;
- proc_arst(mod_it.second, proc_it.second, assign_map);
- if (global_arst.empty() || mod_it.second->wires_.count(global_arst) == 0)
+ proc_arst(mod, proc_it.second, assign_map);
+ if (global_arst.empty() || mod->wire(global_arst) == nullptr)
continue;
std::vector<RTLIL::SigSig> arst_actions;
for (auto sync : proc_it.second->syncs)
@@ -266,7 +271,7 @@ struct ProcArstPass : public Pass {
if (!arst_actions.empty()) {
RTLIL::SyncRule *sync = new RTLIL::SyncRule;
sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1;
- sync->signal = mod_it.second->wires_.at(global_arst);
+ sync->signal = mod->wire(global_arst);
sync->actions = arst_actions;
proc_it.second->syncs.push_back(sync);
}
diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc
index 678d620b..e4c52663 100644
--- a/passes/proc/proc_clean.cc
+++ b/passes/proc/proc_clean.cc
@@ -149,23 +149,23 @@ struct ProcCleanPass : public Pass {
extra_args(args, 1, design);
- for (auto &mod_it : design->modules_) {
+ for (auto mod : design->modules()) {
std::vector<std::string> delme;
- if (!design->selected(mod_it.second))
+ if (!design->selected(mod))
continue;
- for (auto &proc_it : mod_it.second->processes) {
- if (!design->selected(mod_it.second, proc_it.second))
+ for (auto &proc_it : mod->processes) {
+ if (!design->selected(mod, proc_it.second))
continue;
- proc_clean(mod_it.second, proc_it.second, total_count);
+ proc_clean(mod, proc_it.second, total_count);
if (proc_it.second->syncs.size() == 0 && proc_it.second->root_case.switches.size() == 0 &&
proc_it.second->root_case.actions.size() == 0) {
- log("Removing empty process `%s.%s'.\n", mod_it.first.c_str(), proc_it.second->name.c_str());
+ log("Removing empty process `%s.%s'.\n", log_id(mod), proc_it.second->name.c_str());
delme.push_back(proc_it.first);
}
}
for (auto &id : delme) {
- delete mod_it.second->processes[id];
- mod_it.second->processes.erase(id);
+ delete mod->processes[id];
+ mod->processes.erase(id);
}
}
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index 7bd909a6..dc310bde 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -371,12 +371,12 @@ struct ProcDffPass : public Pass {
extra_args(args, 1, design);
- for (auto &mod_it : design->modules_)
- if (design->selected(mod_it.second)) {
- ConstEval ce(mod_it.second);
- for (auto &proc_it : mod_it.second->processes)
- if (design->selected(mod_it.second, proc_it.second))
- proc_dff(mod_it.second, proc_it.second, ce);
+ for (auto mod : design->modules())
+ if (design->selected(mod)) {
+ ConstEval ce(mod);
+ for (auto &proc_it : mod->processes)
+ if (design->selected(mod, proc_it.second))
+ proc_dff(mod, proc_it.second, ce);
}
}
} ProcDffPass;
diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc
index 3607905f..99498505 100644
--- a/passes/proc/proc_init.cc
+++ b/passes/proc/proc_init.cc
@@ -101,11 +101,11 @@ struct ProcInitPass : public Pass {
extra_args(args, 1, design);
- for (auto &mod_it : design->modules_)
- if (design->selected(mod_it.second))
- for (auto &proc_it : mod_it.second->processes)
- if (design->selected(mod_it.second, proc_it.second))
- proc_init(mod_it.second, proc_it.second);
+ for (auto mod : design->modules())
+ if (design->selected(mod))
+ for (auto &proc_it : mod->processes)
+ if (design->selected(mod, proc_it.second))
+ proc_init(mod, proc_it.second);
}
} ProcInitPass;
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index bcbee6cf..fb49182c 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -276,11 +276,11 @@ struct ProcMuxPass : public Pass {
extra_args(args, 1, design);
- for (auto &mod_it : design->modules_)
- if (design->selected(mod_it.second))
- for (auto &proc_it : mod_it.second->processes)
- if (design->selected(mod_it.second, proc_it.second))
- proc_mux(mod_it.second, proc_it.second);
+ for (auto mod : design->modules())
+ if (design->selected(mod))
+ for (auto &proc_it : mod->processes)
+ if (design->selected(mod, proc_it.second))
+ proc_mux(mod, proc_it.second);
}
} ProcMuxPass;
diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc
index e7e4bbc5..9e5f413a 100644
--- a/passes/proc/proc_rmdead.cc
+++ b/passes/proc/proc_rmdead.cc
@@ -79,18 +79,18 @@ struct ProcRmdeadPass : public Pass {
extra_args(args, 1, design);
int total_counter = 0;
- for (auto &mod_it : design->modules_) {
- if (!design->selected(mod_it.second))
+ for (auto mod : design->modules()) {
+ if (!design->selected(mod))
continue;
- for (auto &proc_it : mod_it.second->processes) {
- if (!design->selected(mod_it.second, proc_it.second))
+ for (auto &proc_it : mod->processes) {
+ if (!design->selected(mod, proc_it.second))
continue;
int counter = 0;
for (auto switch_it : proc_it.second->root_case.switches)
proc_rmdead(switch_it, counter);
if (counter > 0)
log("Removed %d dead cases from process %s in module %s.\n", counter,
- proc_it.first.c_str(), mod_it.first.c_str());
+ proc_it.first.c_str(), log_id(mod));
total_counter += counter;
}
}