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authorClifford Wolf <clifford@clifford.at>2014-07-23 09:48:26 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-23 09:52:55 +0200
commitec923652e2eb721aa16657e54a67666f855c3d65 (patch)
tree934ce8ee55c3c58a1e2c11f19eec194665413906 /passes/proc
parenta8d3a68971ccc4e47c54a906aae374a9a54b1415 (diff)
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
Diffstat (limited to 'passes/proc')
-rw-r--r--passes/proc/proc_mux.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index 0fe76573..804c51fd 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -81,7 +81,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1))
{
- mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec::grml(cmp_wire, cmp_wire->width++), sig));
+ mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig));
}
else
{
@@ -103,7 +103,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
eq_cell->connections["\\A"] = sig;
eq_cell->connections["\\B"] = comp;
- eq_cell->connections["\\Y"] = RTLIL::SigSpec::grml(cmp_wire, cmp_wire->width++);
+ eq_cell->connections["\\Y"] = RTLIL::SigSpec(cmp_wire, cmp_wire->width++);
}
}