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authorClifford Wolf <clifford@clifford.at>2014-07-27 01:49:51 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 01:49:51 +0200
commitf9946232adf887e5aa4a48c64f88eaa17e424009 (patch)
tree39594b3287c3369752668456c4a6b1735fb66e77 /passes/proc
parentd7916a49aff3c47b7c1ce07abe3b6e3d5714079b (diff)
Refactoring: Renamed RTLIL::Module::wires to wires_
Diffstat (limited to 'passes/proc')
-rw-r--r--passes/proc/proc_arst.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index 114f2567..565d86a7 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -243,7 +243,7 @@ struct ProcArstPass : public Pass {
if (!design->selected(mod_it.second, proc_it.second))
continue;
proc_arst(mod_it.second, proc_it.second, assign_map);
- if (global_arst.empty() || mod_it.second->wires.count(global_arst) == 0)
+ if (global_arst.empty() || mod_it.second->wires_.count(global_arst) == 0)
continue;
std::vector<RTLIL::SigSig> arst_actions;
for (auto sync : proc_it.second->syncs)
@@ -266,7 +266,7 @@ struct ProcArstPass : public Pass {
if (!arst_actions.empty()) {
RTLIL::SyncRule *sync = new RTLIL::SyncRule;
sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1;
- sync->signal = mod_it.second->wires.at(global_arst);
+ sync->signal = mod_it.second->wires_.at(global_arst);
sync->actions = arst_actions;
proc_it.second->syncs.push_back(sync);
}