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authorClifford Wolf <clifford@clifford.at>2014-07-23 15:36:09 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-23 15:36:09 +0200
commit4e802eb7f6fe5858f8657be7cd3e6638cc0f2ece (patch)
tree917ce7eece77475cfc632f3d41f5fb8aadef64d2 /passes/sat/eval.cc
parent85db102e13bbd6decda3f99ef640d0991ee24b33 (diff)
Fixed all users of SigSpec::chunks_rw() and removed it
Diffstat (limited to 'passes/sat/eval.cc')
-rw-r--r--passes/sat/eval.cc14
1 files changed, 6 insertions, 8 deletions
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index 902dedb6..090f7463 100644
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -70,11 +70,9 @@ struct BruteForceEquivChecker
log_signal(undef2), log_signal(mod1_inputs), log_signal(inputs));
if (ignore_x_mod1) {
- sig1.expand(), sig2.expand();
- for (size_t i = 0; i < sig1.chunks().size(); i++)
- if (sig1.chunks().at(i) == RTLIL::SigChunk(RTLIL::State::Sx))
- sig2.chunks_rw().at(i) = RTLIL::SigChunk(RTLIL::State::Sx);
- sig1.optimize(), sig2.optimize();
+ for (int i = 0; i < SIZE(sig1); i++)
+ if (sig1[i] == RTLIL::State::Sx)
+ sig2[i] = RTLIL::State::Sx;
}
if (sig1 != sig2) {
@@ -297,9 +295,9 @@ struct VlogHammerReporter
sig.expand();
if (rtl_sig.size() != sig.size())
log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name));
- for (int i = 0; i < sig.size(); i++)
- if (rtl_sig.chunks().at(i).data.bits.at(0) == RTLIL::State::Sx)
- sig.chunks_rw().at(i).data.bits.at(0) = RTLIL::State::Sx;
+ for (int i = 0; i < SIZE(sig); i++)
+ if (rtl_sig[i] == RTLIL::State::Sx)
+ sig[i] = RTLIL::State::Sx;
}
log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str());