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| author | Clifford Wolf <clifford@clifford.at> | 2013-06-08 14:11:50 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-06-08 14:11:50 +0200 |
| commit | 1434312fdd1290ac21eb57c79c1999e775cdba54 (patch) | |
| tree | 983363203e4430851b2f01b5e715f8e6b30b394b /passes/sat/example.ys | |
| parent | 99957a825f077248560b8232465b61d1c2416cfc (diff) | |
Various improvements in sat_solve pass and SAT generator
Diffstat (limited to 'passes/sat/example.ys')
| -rw-r--r-- | passes/sat/example.ys | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/passes/sat/example.ys b/passes/sat/example.ys index b6d131c9..d4037f78 100644 --- a/passes/sat/example.ys +++ b/passes/sat/example.ys @@ -1,3 +1,5 @@ read_verilog example.v -techmap; opt; abc; opt -sat_solve -set y 1'b1 +proc; opt_clean +sat_solve -set y 1'b1 example001 +sat_solve -set y 1'b1 example002 +sat_solve -set y 1'b1 example003 |