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| author | Clifford Wolf <clifford@clifford.at> | 2013-06-07 13:59:13 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-06-07 13:59:13 +0200 |
| commit | 46fbe9d26299a7b6197463b3056d778f525658fb (patch) | |
| tree | 748b515d870f60b047e77e4b3e93257a116ccb46 /passes/sat/example.ys | |
| parent | 3371563f2f14ce0d6bc7798d0fc802b54aae93c8 (diff) | |
Added SAT generator and simple sat_solve command
Diffstat (limited to 'passes/sat/example.ys')
| -rw-r--r-- | passes/sat/example.ys | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/sat/example.ys b/passes/sat/example.ys new file mode 100644 index 00000000..b7798ab2 --- /dev/null +++ b/passes/sat/example.ys @@ -0,0 +1,3 @@ +read_verilog example.v +techmap; opt +sat_solve -show a -set y 1'b1 |