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author | Clifford Wolf <clifford@clifford.at> | 2013-06-07 14:37:33 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-06-07 14:37:33 +0200 |
commit | 56b593b91cc693849e3b3b3de0666f6ec9a597f6 (patch) | |
tree | ccaa7c501a228f4056b887370682f054c81aea48 /passes/sat/example.ys | |
parent | 46fbe9d26299a7b6197463b3056d778f525658fb (diff) |
Improved sat generator and sat_solve pass
Diffstat (limited to 'passes/sat/example.ys')
-rw-r--r-- | passes/sat/example.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/example.ys b/passes/sat/example.ys index b7798ab2..e2eb1749 100644 --- a/passes/sat/example.ys +++ b/passes/sat/example.ys @@ -1,3 +1,3 @@ read_verilog example.v -techmap; opt +techmap; opt; abc; opt sat_solve -show a -set y 1'b1 |