diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 11:58:03 +0200 |
---|---|---|
committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 11:58:03 +0200 |
commit | cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 (patch) | |
tree | 2d417ab32f95d109a0d8438ae7a14acf51783c5b /passes/sat/freduce.cc | |
parent | 665759fceee4a0db3e776b7912e976eea2ff29a3 (diff) |
Renamed RTLIL::{Module,Cell}::connections to connections_
Diffstat (limited to 'passes/sat/freduce.cc')
-rw-r--r-- | passes/sat/freduce.cc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 79dec3b5..517e6713 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -610,7 +610,7 @@ struct FreduceWorker for (auto &it : module->cells) { if (ct.cell_known(it.second->type)) { std::set<RTLIL::SigBit> inputs, outputs; - for (auto &port : it.second->connections) { + for (auto &port : it.second->connections_) { std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector(); if (ct.cell_output(it.second->type, port.first)) outputs.insert(bits.begin(), bits.end()); @@ -624,7 +624,7 @@ struct FreduceWorker bits_full_total += outputs.size(); } if (inv_mode && it.second->type == "$_INV_") - inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->connections.at("\\A")), sigmap(it.second->connections.at("\\Y")))); + inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->connections_.at("\\A")), sigmap(it.second->connections_.at("\\Y")))); } int bits_count = 0; @@ -708,7 +708,7 @@ struct FreduceWorker RTLIL::Cell *drv = drivers.at(grp[i].bit).first; RTLIL::Wire *dummy_wire = module->addWire(NEW_ID); - for (auto &port : drv->connections) + for (auto &port : drv->connections_) if (ct.cell_output(drv->type, port.first)) sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second); @@ -719,14 +719,14 @@ struct FreduceWorker inv_sig = module->addWire(NEW_ID); RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_"); - inv_cell->connections["\\A"] = grp[0].bit; - inv_cell->connections["\\Y"] = inv_sig; + inv_cell->connections_["\\A"] = grp[0].bit; + inv_cell->connections_["\\Y"] = inv_sig; } - module->connections.push_back(RTLIL::SigSig(grp[i].bit, inv_sig)); + module->connections_.push_back(RTLIL::SigSig(grp[i].bit, inv_sig)); } else - module->connections.push_back(RTLIL::SigSig(grp[i].bit, grp[0].bit)); + module->connections_.push_back(RTLIL::SigSig(grp[i].bit, grp[0].bit)); rewired_sigbits++; } |