added log_header to miter and expose pass, show cell type for exposed ports

1 files changed, 4 insertions, 0 deletions

diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index db12cb57..6c8e2ff4 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -28,6 +28,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 	bool flag_make_outcmp = false;
 	bool flag_make_assert = false;
 
+	log_header("Executing MITER pass (creating miter circuit).\n");
+
 	size_t argidx;
 	for (argidx = 2; argidx < args.size(); argidx++)
 	{
@@ -102,6 +104,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 		log_cmd_error("No matching port in gold module was found for %s!\n", it.second->name.c_str());
 	}
 
+	log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name));
+
 	RTLIL::Module *miter_module = new RTLIL::Module;
 	miter_module->name = miter_name;
 	design->modules[miter_name] = miter_module;