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authorClifford Wolf <clifford@clifford.at>2014-07-23 10:05:42 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-23 10:05:42 +0200
commit5b51b67297a5e5e20cbe2b015b584aee4c30489f (patch)
tree934ce8ee55c3c58a1e2c11f19eec194665413906 /passes/sat/miter.cc
parentc61467a32c4bd3ec4b9e0cb6d36d602f0e4dea81 (diff)
parentec923652e2eb721aa16657e54a67666f855c3d65 (diff)
Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor
Diffstat (limited to 'passes/sat/miter.cc')
-rw-r--r--passes/sat/miter.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 79857c5e..12384e2c 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -174,7 +174,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
eqx_cell->parameters["\\Y_WIDTH"] = 1;
eqx_cell->parameters["\\A_SIGNED"] = 0;
eqx_cell->parameters["\\B_SIGNED"] = 0;
- eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, 1, i);
+ eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, i);
eqx_cell->connections["\\B"] = RTLIL::State::Sx;
eqx_cell->connections["\\Y"] = gold_x.extract(i, 1);
miter_module->add(eqx_cell);