diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 08:40:31 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 09:49:43 +0200 |
| commit | a8d3a68971ccc4e47c54a906aae374a9a54b1415 (patch) | |
| tree | ed08831d07df4e799d881349c36acf76bf277791 /passes/sat/miter.cc | |
| parent | 260c19ec5a3adb292158658dd69a352b9325ab64 (diff) | |
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Diffstat (limited to 'passes/sat/miter.cc')
| -rw-r--r-- | passes/sat/miter.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 79857c5e..51cf3ae0 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -174,7 +174,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, eqx_cell->parameters["\\Y_WIDTH"] = 1; eqx_cell->parameters["\\A_SIGNED"] = 0; eqx_cell->parameters["\\B_SIGNED"] = 0; - eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, 1, i); + eqx_cell->connections["\\A"] = RTLIL::SigSpec::grml(w2_gold, i); eqx_cell->connections["\\B"] = RTLIL::State::Sx; eqx_cell->connections["\\Y"] = gold_x.extract(i, 1); miter_module->add(eqx_cell); |