diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-07-25 15:05:18 +0200 |
---|---|---|
committer | Clifford Wolf <clifford@clifford.at> | 2014-07-25 17:56:19 +0200 |
commit | 2bec47a4045d23d46e7d300cbf80b2dce1a549a9 (patch) | |
tree | 991a75afe9b009486a57834fefee075ec695a28c /passes/sat/share.cc | |
parent | 5826670009e1018734de49aaf1554cb8a43d09d7 (diff) |
Use only module->addCell() and module->remove() to create and delete cells
Diffstat (limited to 'passes/sat/share.cc')
-rw-r--r-- | passes/sat/share.cc | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/passes/sat/share.cc b/passes/sat/share.cc index ede2fa88..7e24e1f0 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -282,15 +282,12 @@ struct ShareWorker RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::Wire *y = module->addWire(NEW_ID, y_width); - RTLIL::Cell *supercell = new RTLIL::Cell; - supercell->name = NEW_ID; - supercell->type = c1->type; + RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); supercell->parameters["\\A_SIGNED"] = a_signed; supercell->parameters["\\A_WIDTH"] = a_width; supercell->parameters["\\Y_WIDTH"] = y_width; supercell->connections["\\A"] = a; supercell->connections["\\Y"] = y; - module->add(supercell); RTLIL::SigSpec new_y1(y, 0, y1.size()); RTLIL::SigSpec new_y2(y, 0, y2.size()); @@ -846,8 +843,7 @@ struct ShareWorker log("Removing %d cells in module %s:\n", SIZE(cells_to_remove), log_id(module)); for (auto c : cells_to_remove) { log(" Removing cell %s (%s).\n", log_id(c), log_id(c->type)); - module->cells.erase(c->name); - delete c; + module->remove(c); } } |