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authorClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
commit4c4b6021562c598c4510831bd547edaa97d14dac (patch)
tree7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /passes/sat/share.cc
parentf9946232adf887e5aa4a48c64f88eaa17e424009 (diff)
Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'passes/sat/share.cc')
-rw-r--r--passes/sat/share.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/sat/share.cc b/passes/sat/share.cc
index 0ee5af18..facacf19 100644
--- a/passes/sat/share.cc
+++ b/passes/sat/share.cc
@@ -61,7 +61,7 @@ struct ShareWorker
queue_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end());
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
if (!fwd_ct.cell_known(it.second->type)) {
std::set<RTLIL::SigBit> &bits = modwalker.cell_inputs[it.second];
queue_bits.insert(bits.begin(), bits.end());
@@ -101,7 +101,7 @@ struct ShareWorker
void find_shareable_cells()
{
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;