Manual fixes for new cell connections API

4 files changed, 21 insertions, 12 deletions

diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 58dcf915..a84faf79 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -485,12 +485,12 @@ struct ExposePass : public Pass {
 				for (auto &it : module->cells) {
 					if (!ct.cell_known(it.second->type))
 						continue;
-					for (auto &conn : it.second->connections())
+					for (auto &conn : it.second->connections_)
 						if (ct.cell_input(it.second->type, conn.first))
 							conn.second = out_to_in_map(sigmap(conn.second));
 				}
 
-				for (auto &conn : module->connections())
+				for (auto &conn : module->connections_)
 					conn.second = out_to_in_map(sigmap(conn.second));
 			}
 
@@ -518,7 +518,7 @@ struct ExposePass : public Pass {
 					for (auto &bit : cell_q_bits)
 						if (wire_bits_set.count(bit))
 							bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++);
-					cell->get("\\Q") = cell_q_bits;
+					cell->set("\\Q", cell_q_bits);
 				}
 
 				RTLIL::Wire *wire_q = new RTLIL::Wire;
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index da934585..d5336ca0 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -708,7 +708,7 @@ struct FreduceWorker
 
 				RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
 				RTLIL::Wire *dummy_wire = module->addWire(NEW_ID);
-				for (auto &port : drv->connections())
+				for (auto &port : drv->connections_)
 					if (ct.cell_output(drv->type, port.first))
 						sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
 
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 34355122..96aa10ba 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -132,8 +132,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 			w2->width = w1->width;
 			miter_module->add(w2);
 
-			gold_cell->connections()[w1->name] = w2;
-			gate_cell->connections()[w1->name] = w2;
+			gold_cell->set(w1->name, w2);
+			gate_cell->set(w1->name, w2);
 		}
 
 		if (w1->port_output)
@@ -150,8 +150,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 			w2_gate->width = w1->width;
 			miter_module->add(w2_gate);
 
-			gold_cell->connections()[w1->name] = w2_gold;
-			gate_cell->connections()[w1->name] = w2_gate;
+			gold_cell->set(w1->name, w2_gold);
+			gate_cell->set(w1->name, w2_gate);
 
 			RTLIL::SigSpec this_condition;
 
diff --git a/passes/sat/share.cc b/passes/sat/share.cc
index 13ef695e..0ee5af18 100644
--- a/passes/sat/share.cc
+++ b/passes/sat/share.cc
@@ -258,7 +258,9 @@ struct ShareWorker
 				RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
 				if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
 					unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1;
-					unsigned_cell->get("\\A").append_bit(RTLIL::State::S0);
+					RTLIL::SigSpec new_a = unsigned_cell->get("\\A");
+					new_a.append_bit(RTLIL::State::S0);
+					unsigned_cell->set("\\A", new_a);
 				}
 				unsigned_cell->parameters.at("\\A_SIGNED") = true;
 				unsigned_cell->check();
@@ -312,7 +314,10 @@ struct ShareWorker
 
 				if (score_flipped < score_unflipped)
 				{
-					std::swap(c2->get("\\A"), c2->get("\\B"));
+					RTLIL::SigSpec tmp = c2->get("\\A");
+					c2->set("\\A", c2->get("\\B"));
+					c2->set("\\B", tmp);
+
 					std::swap(c2->parameters.at("\\A_WIDTH"), c2->parameters.at("\\B_WIDTH"));
 					std::swap(c2->parameters.at("\\A_SIGNED"), c2->parameters.at("\\B_SIGNED"));
 					modified_src_cells = true;
@@ -325,7 +330,9 @@ struct ShareWorker
 				RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
 				if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
 					unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1;
-					unsigned_cell->get("\\A").append_bit(RTLIL::State::S0);
+					RTLIL::SigSpec new_a = unsigned_cell->get("\\A");
+					new_a.append_bit(RTLIL::State::S0);
+					unsigned_cell->set("\\A", new_a);
 				}
 				unsigned_cell->parameters.at("\\A_SIGNED") = true;
 				modified_src_cells = true;
@@ -336,7 +343,9 @@ struct ShareWorker
 				RTLIL::Cell *unsigned_cell = c1->parameters.at("\\B_SIGNED").as_bool() ? c2 : c1;
 				if (unsigned_cell->get("\\B").to_sigbit_vector().back() != RTLIL::State::S0) {
 					unsigned_cell->parameters.at("\\B_WIDTH") = unsigned_cell->parameters.at("\\B_WIDTH").as_int() + 1;
-					unsigned_cell->get("\\B").append_bit(RTLIL::State::S0);
+					RTLIL::SigSpec new_b = unsigned_cell->get("\\B");
+					new_b.append_bit(RTLIL::State::S0);
+					unsigned_cell->set("\\B", new_b);
 				}
 				unsigned_cell->parameters.at("\\B_SIGNED") = true;
 				modified_src_cells = true;