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authorClifford Wolf <clifford@clifford.at>2014-07-23 10:05:42 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-23 10:05:42 +0200
commit5b51b67297a5e5e20cbe2b015b584aee4c30489f (patch)
tree934ce8ee55c3c58a1e2c11f19eec194665413906 /passes/sat
parentc61467a32c4bd3ec4b9e0cb6d36d602f0e4dea81 (diff)
parentec923652e2eb721aa16657e54a67666f855c3d65 (diff)
Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor
Diffstat (limited to 'passes/sat')
-rw-r--r--passes/sat/eval.cc4
-rw-r--r--passes/sat/miter.cc2
-rw-r--r--passes/sat/share.cc10
3 files changed, 8 insertions, 8 deletions
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index 73235e93..902dedb6 100644
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -260,8 +260,8 @@ struct VlogHammerReporter
for (int i = 0; i < int(inputs.size()); i++) {
RTLIL::Wire *wire = module->wires.at(inputs[i]);
for (int j = input_widths[i]-1; j >= 0; j--) {
- ce.set(RTLIL::SigSpec(wire, 1, j), bits.back());
- recorded_set_vars.append(RTLIL::SigSpec(wire, 1, j));
+ ce.set(RTLIL::SigSpec(wire, j), bits.back());
+ recorded_set_vars.append(RTLIL::SigSpec(wire, j));
recorded_set_vals.bits.push_back(bits.back());
bits.pop_back();
}
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 79857c5e..12384e2c 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -174,7 +174,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
eqx_cell->parameters["\\Y_WIDTH"] = 1;
eqx_cell->parameters["\\A_SIGNED"] = 0;
eqx_cell->parameters["\\B_SIGNED"] = 0;
- eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, 1, i);
+ eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, i);
eqx_cell->connections["\\B"] = RTLIL::State::Sx;
eqx_cell->connections["\\Y"] = gold_x.extract(i, 1);
miter_module->add(eqx_cell);
diff --git a/passes/sat/share.cc b/passes/sat/share.cc
index 738b0bd6..ede2fa88 100644
--- a/passes/sat/share.cc
+++ b/passes/sat/share.cc
@@ -292,8 +292,8 @@ struct ShareWorker
supercell->connections["\\Y"] = y;
module->add(supercell);
- RTLIL::SigSpec new_y1(y, y1.size());
- RTLIL::SigSpec new_y2(y, y2.size());
+ RTLIL::SigSpec new_y1(y, 0, y1.size());
+ RTLIL::SigSpec new_y2(y, 0, y2.size());
module->connections.push_back(RTLIL::SigSig(y1, new_y1));
module->connections.push_back(RTLIL::SigSig(y2, new_y2));
@@ -405,8 +405,8 @@ struct ShareWorker
supercell->connections["\\Y"] = y;
supercell->check();
- RTLIL::SigSpec new_y1(y, y1.size());
- RTLIL::SigSpec new_y2(y, y2.size());
+ RTLIL::SigSpec new_y1(y, 0, y1.size());
+ RTLIL::SigSpec new_y2(y, 0, y2.size());
module->connections.push_back(RTLIL::SigSig(y1, new_y1));
module->connections.push_back(RTLIL::SigSig(y2, new_y2));
@@ -620,7 +620,7 @@ struct ShareWorker
RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0);
for (auto &p : activation_patterns) {
all_cases_wire->width++;
- module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, 1, all_cases_wire->width - 1));
+ module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, all_cases_wire->width - 1));
}
if (all_cases_wire->width == 1)
return all_cases_wire;