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authorClifford Wolf <clifford@clifford.at>2014-08-15 14:11:40 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-15 14:11:40 +0200
commitf092b5014895dc5dc62b8103fcedf94cfa9f85a8 (patch)
tree2f09add560746030249fe333e551de2f113bccdb /passes/sat
parentbf486002d9a6d976b3d086700ccdcfb0fb70ba0b (diff)
Renamed $_INV_ cell type to $_NOT_
Diffstat (limited to 'passes/sat')
-rw-r--r--passes/sat/freduce.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index 7b9fb207..bfed0005 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -623,7 +623,7 @@ struct FreduceWorker
batches.push_back(outputs);
bits_full_total += outputs.size();
}
- if (inv_mode && it.second->type == "$_INV_")
+ if (inv_mode && it.second->type == "$_NOT_")
inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->getPort("\\A")), sigmap(it.second->getPort("\\Y"))));
}
@@ -718,7 +718,7 @@ struct FreduceWorker
{
inv_sig = module->addWire(NEW_ID);
- RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_");
+ RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_NOT_");
inv_cell->setPort("\\A", grp[0].bit);
inv_cell->setPort("\\Y", inv_sig);
}