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authorClifford Wolf <clifford@clifford.at>2015-10-25 19:30:49 +0100
committerClifford Wolf <clifford@clifford.at>2015-10-25 19:30:49 +0100
commit207736b4ee0363ff6714071e64024965916eafc2 (patch)
tree31092cfab4323500bc491d8b59deee9e297730d0 /passes/techmap/abc.cc
parentda923c198e770806a4abb749acc75fa337247920 (diff)
Import more std:: stuff into Yosys namespace
Diffstat (limited to 'passes/techmap/abc.cc')
-rw-r--r--passes/techmap/abc.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 64586927..70677988 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1399,7 +1399,7 @@ struct AbcPass : public Pass {
std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
- typedef std::tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
+ typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
std::map<clkdomain_t, std::vector<RTLIL::Cell*>> assigned_cells;
std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse;