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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2016-11-03 23:18:00 +0100 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2016-11-03 23:18:00 +0100 |
| commit | fefe0fc0430f4f173a25e674708aa0f4f0854b31 (patch) | |
| tree | adb13b830212c269d58031f900d652f29013d2d7 /passes/techmap/attrmvcp.cc | |
| parent | 4f096fe65b77435daba019248273e547fa18d167 (diff) | |
Imported yosys 0.7
Diffstat (limited to 'passes/techmap/attrmvcp.cc')
| -rw-r--r-- | passes/techmap/attrmvcp.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/techmap/attrmvcp.cc b/passes/techmap/attrmvcp.cc index 50eaf61d..1537def0 100644 --- a/passes/techmap/attrmvcp.cc +++ b/passes/techmap/attrmvcp.cc @@ -93,6 +93,7 @@ struct AttrmvcpPass : public Pass { for (auto cell : module->selected_cells()) for (auto &conn : cell->connections()) + { if (driven_mode) { if (cell->input(conn.first)) for (auto bit : sigmap(conn.second)) @@ -102,6 +103,7 @@ struct AttrmvcpPass : public Pass { for (auto bit : sigmap(conn.second)) net2cells[bit].insert(cell); } + } for (auto wire : module->selected_wires()) { |