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authorClifford Wolf <clifford@clifford.at>2015-01-16 17:51:17 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-16 17:51:17 +0100
commit8ce8a230f458d09f1847ba87a3073cf4c07579d3 (patch)
treeaa9d82463cef09777d0911953b7cb5f31da9ad3c /passes/techmap/dff2dffe.cc
parent3ed4e34380036c63d6177f41f43767b41201e4a8 (diff)
Bugfix in dff2dffe
Diffstat (limited to 'passes/techmap/dff2dffe.cc')
-rw-r--r--passes/techmap/dff2dffe.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index 33900715..17549bd0 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -173,7 +173,7 @@ struct Dff2dffeWorker
return or_input;
RTLIL::SigSpec y = module->addWire(NEW_ID);
- RTLIL::Cell *c = module->addReduceOr(NEW_ID, or_input, y);
+ RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y);
if (make_gates) {
simplemap(module, c);