summaryrefslogtreecommitdiff
path: root/passes/techmap/dffinit.cc
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2015-10-25 19:30:49 +0100
committerClifford Wolf <clifford@clifford.at>2015-10-25 19:30:49 +0100
commit207736b4ee0363ff6714071e64024965916eafc2 (patch)
tree31092cfab4323500bc491d8b59deee9e297730d0 /passes/techmap/dffinit.cc
parentda923c198e770806a4abb749acc75fa337247920 (diff)
Import more std:: stuff into Yosys namespace
Diffstat (limited to 'passes/techmap/dffinit.cc')
-rw-r--r--passes/techmap/dffinit.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc
index 84770ff3..6a80f043 100644
--- a/passes/techmap/dffinit.cc
+++ b/passes/techmap/dffinit.cc
@@ -68,7 +68,7 @@ struct DffinitPass : public Pass {
for (auto wire : module->selected_wires()) {
if (wire->attributes.count("\\init")) {
Const value = wire->attributes.at("\\init");
- for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++)
+ for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
init_bits[sigmap(SigBit(wire, i))] = value[i];
}
if (wire->port_output)
@@ -116,7 +116,7 @@ struct DffinitPass : public Pass {
if (wire->attributes.count("\\init")) {
Const &value = wire->attributes.at("\\init");
bool do_cleanup = true;
- for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++) {
+ for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
SigBit bit = sigmap(SigBit(wire, i));
if (cleanup_bits.count(bit) || !used_bits.count(bit))
value[i] = State::Sx;