diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
| commit | 4c4b6021562c598c4510831bd547edaa97d14dac (patch) | |
| tree | 7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /passes/techmap/dfflibmap.cc | |
| parent | f9946232adf887e5aa4a48c64f88eaa17e424009 (diff) | |
Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'passes/techmap/dfflibmap.cc')
| -rw-r--r-- | passes/techmap/dfflibmap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index eabc56bd..01284656 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -388,7 +388,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) log("Mapping DFF cells in module `%s':\n", module->name.c_str()); std::vector<RTLIL::Cell*> cell_list; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0) cell_list.push_back(it.second); } |