diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 15:36:09 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 15:36:09 +0200 |
commit | 4e802eb7f6fe5858f8657be7cd3e6638cc0f2ece (patch) | |
tree | 917ce7eece77475cfc632f3d41f5fb8aadef64d2 /passes/techmap/extract.cc | |
parent | 85db102e13bbd6decda3f99ef640d0991ee24b33 (diff) |
Fixed all users of SigSpec::chunks_rw() and removed it
Diffstat (limited to 'passes/techmap/extract.cc')
-rw-r--r-- | passes/techmap/extract.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 1687a1ff..e5055c9c 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -755,11 +755,11 @@ struct ExtractPass : public Pass { newCell->type = cell->type; newCell->parameters = cell->parameters; for (auto &conn : cell->connections) { - RTLIL::SigSpec sig = sigmap(conn.second); - for (auto &chunk : sig.chunks_rw()) + std::vector<RTLIL::SigChunk> chunks = sigmap(conn.second); + for (auto &chunk : chunks) if (chunk.wire != NULL) chunk.wire = newMod->wires.at(chunk.wire->name); - newCell->connections[conn.first] = sig; + newCell->connections[conn.first] = chunks; } newMod->add(newCell); } |