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authorClifford Wolf <clifford@clifford.at>2014-07-27 10:18:00 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 11:18:30 +0200
commit10e5791c5e5660cb784503d36439ee90d61eb06b (patch)
treed7bd3d8f1d0254e14fcf68ce25545f42afab9724 /passes/techmap/extract.cc
parentd088854b47f5f77c6a62be2ba4b895164938d7a2 (diff)
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'passes/techmap/extract.cc')
-rw-r--r--passes/techmap/extract.cc12
1 files changed, 6 insertions, 6 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index b66a11b8..8587f53b 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -604,9 +604,9 @@ struct ExtractPass : public Pass {
delete map;
log_cmd_error("Can't saved design `%s'.\n", filename.c_str()+1);
}
- for (auto &it : saved_designs.at(filename.substr(1))->modules)
- if (!map->modules.count(it.first))
- map->modules[it.first] = it.second->clone();
+ for (auto &it : saved_designs.at(filename.substr(1))->modules_)
+ if (!map->modules_.count(it.first))
+ map->modules_[it.first] = it.second->clone();
}
else
{
@@ -632,7 +632,7 @@ struct ExtractPass : public Pass {
log_header("Creating graphs for SubCircuit library.\n");
if (!mine_mode)
- for (auto &mod_it : map->modules) {
+ for (auto &mod_it : map->modules_) {
SubCircuit::Graph mod_graph;
std::string graph_name = "needle_" + RTLIL::unescape_id(mod_it.first);
log("Creating needle graph %s.\n", graph_name.c_str());
@@ -643,7 +643,7 @@ struct ExtractPass : public Pass {
}
}
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
SubCircuit::Graph mod_graph;
std::string graph_name = "haystack_" + RTLIL::unescape_id(mod_it.first);
log("Creating haystack graph %s.\n", graph_name.c_str());
@@ -725,7 +725,7 @@ struct ExtractPass : public Pass {
RTLIL::Module *newMod = new RTLIL::Module;
newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
- map->modules[newMod->name] = newMod;
+ map->modules_[newMod->name] = newMod;
int portCounter = 1;
for (auto wire : wires) {